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| SL74HC75 Dual 2-Bit Transparent Latch High-Performance Silicon-Gate CMOS The SL74HC75 is identical in pinout to the LS/ALS75. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 2-bit transparent latches and can be used as temporary storage for binary information between processing units and input/output or indicator units. Each latch stores the input data while Latch Enable is at a logic low. The outputs follow the data inputs when Latch Enable is at a logic high. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC75N Plastic SL74HC75D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 5=VCC PIN 12 = GND D L H X Inputs Latch Enable H H L Outputs Q L H Q0 Q H L Q0 X = Don't Care Q0 = latched data SLS System Logic Semiconductor SL74HC75 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC75 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 4.0 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 40 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 80 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT 20 A VIN= VIL or VIH IOUT 4.0 mA IOUT 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0A SLS System Logic Semiconductor SL74HC75 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, D to Q (Figures 1 and 5) Maximum Propagation Delay , D to Q (Figures 1 and 5) Maximum Propagation Delay ,Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay ,Latch Enable to Q (Figures 2 and 5) Maximum Output Transition Time, Any Output (Figures 3 and 5) Maximum Input Capacitance Power Dissipation Capacitance (Per Latch) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 125 25 21 110 22 19 145 29 25 125 25 21 75 15 13 10 85C 155 31 26 140 28 24 180 36 31 155 31 26 95 19 16 10 125C 190 38 32 165 33 28 220 44 38 190 38 32 110 22 19 10 Unit ns tPLH, t PHL ns tPLH, t PHL ns tPLH, t PHL ns tTLH, tTHL ns CIN pF Typical @25C,VCC=5.0 V 35 pF TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tSU Parameter Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum Hold Time,Latch Enable to D (Figure 4) Minimum Pulse Width, Latch Enable Input (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 25 C to -55C 100 20 17 25 5 5 80 16 14 1000 500 400 Guaranteed Limit 85C 125 25 21 30 6 6 100 20 17 1000 500 400 125C 150 30 26 40 8 7 120 24 20 1000 500 400 Unit ns th ns tw ns tr, tf ns SLS System Logic Semiconductor SL74HC75 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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